The invention relates to sense amplifier circuits and, in particular, to current sense amplifier circuits for sensing current change on a signal line.
A CMOS image sensor with pixel level analog-to-digital conversion is described in U.S. Pat. No. 5,461,425 of B. Fowler et al. (the ""425 patent). Such an image sensor, referred to as a digital pixel sensor (DPS), provides a digital output signal at each pixel element representing the light intensity detected by that pixel element. The combination of a photodetector and an analog-to-digital (A/D) converter in an area image sensor helps enhance detection accuracy, reduce power consumption, and improves overall system performance.
One of the components in a DPS system is analog circuitry used to convert the photodetector voltage to a digital value. The analog circuitry is sensitive to the noise that digital signals can generate as the digital signal changes state. The amount of noise generated by a digital signal is a direct function of the voltage swing of the signal. One of the noisier digital signals in a DPS system is the bit line read out. In conventional image sensors including a two dimensional array of pixel elements, a bit line is coupled to a column of pixel elements to read out the digital value from a selected pixel element. The bit lines are typically precharged to a predetermined voltage and the bit line voltage is forced to a second voltage level depending on the digital value of the cell to be read out. A sense amplifier coupled to the bit line detects the change in voltage to determine the logical value of the bit line voltage. Thus, the bit line signal is typically associated with a large voltage swing, introducing undesirable noise to the image sensor.
Therefore, rather than sensing a voltage transition on the bit line, it is desirable to sense a current transition on the bit line while holding the bit line voltage at a constant. By holding the bit line voltage constant, noise within an image sensor associated with bit line voltage swing can be minimized. When current sensing is employed, the logical state of the bit line readout is determined either by the presence (digital 1) or lack (digital 0) of bit line current. To facilitate bit line current sensing, a current mode sense amplifier, or current sense amplifier, is needed.
FIG. 1 is a circuit diagram of a conventional current sense amplifier. Current sense amplifier 10 includes a high speed differential input operational amplifier configured as an integrator. That is, an integrating capacitor Cinteg is coupled across the output terminal and the negative input terminal of the operational amplifier. The integrator is reset at the beginning of each clock cycle with a short pulse. Specifically, a pulse generated by the pulse generator causes a transistor 12 to turn on to discharge capacitor Cinteg. In operation, the bit line current, if present, will charge up capacitor Cinteg. If the output of the integrator exceeds the logic threshold of the D-input to the flip flop before the next clock edge, a logical xe2x80x9c1xe2x80x9d is asserted at the output of the flip flop, otherwise a logical xe2x80x9c0xe2x80x9d is asserted. The positive input of the operational amplifier is held at a reference voltage Vr sufficiently large to insure a minimum bit line current. However, the reference voltage Vr must also be sufficiently small to guarantee that it is below the logic low input threshold of the flip flop. Thus, a complicated biasing scheme is required to guarantee all the operation conditions.
Current sense amplifier 10 of FIG. 1 will hold the bit line voltage at a constant as long as the output of the operational amplifier is free to move (that is, not limited by the power supply rail) and as long as the operational amplifier is not slew rate or band limited. These are all difficult requirements to meet and thus the current sense amplifier circuit shown in FIG. 1 usually cannot hold the bit line voltage constant within a reasonable range.
Conventional current sense amplifiers are not satisfactory because they typically are not capable of holding the bit line voltage constant within a reasonable range. When the circuit in FIG. 1 is used, a complicated differential operational amplifier is needed.
It is therefore desirable to provide a current sense amplifier for performing bit line current sensing that can be implemented using relatively simple circuitry and can hold the bit line voltage constant without limitations.
According to one embodiment of the present invention, a current sense amplifier circuit coupled to detect a first current flowing in a first node includes an input gain stage incorporating a feedback loop, a current mirror, a charge integration stage and a comparator. The first current is coupled to an input node of the input gain stage where the input gain stage operates to maintain the voltage at the input node at a substantially constant level. The current mirror is coupled to an output node of the input gain stage to mirror the first current into a second current. The charge integration stage is coupled to integrate charge associated with the second current to develop a first voltage. Finally, the comparator is coupled to compare the first voltage to a reference level and providing an output signal at an output terminal. In operation, the comparator generates an output signal having a first value when the first current exceeds a predetermined threshold level and a second value when the first current is less than the predetermined threshold level. In one embodiment, the comparator is implemented as a Schmitt trigger.
The present invention is better understood upon consideration of the detailed description below and the accompanying drawings.